Initial population structure of HS is very similar to that of DE as explained in the previous subsection. Here, the total

number of individuals is equal to harmony memory size (HMS) and individuals are stored in harmony memory (HM). Following, a new solution is improvised according to harmony memory considering rate (HMCR). A stored value is chosen from HM with probability of HMCR (0≤HMCR≤

1) and 1-HMCR is the probability of generating it randomly. If the solution is picked from HM, it is mutated according to the pitch adjust rate (0≤PAR≤ 1). After HM is updated the fitness values are evaluated. If the improvised solution yields a better fitness than that of the worst member in HM, it replaces the worst one. Otherwise the improvised one is eliminated. The above procedure is repeated until a preset termination criterion (maximum iterations or a target fitness value) is met [13].

C. Artificial Bee Colony ABC algorithm is a recently introduced optimization algorithm and simulates the foraging behavior of bee colony [14]. Position of a food source represents a possible solution

to the optimization problem and the nectar amount of a food

source corresponds to the quality (fitness) of the associated

solution. First of all, the food source positions are randomly initialized as xi (i=1,…,SN) where SN is the maximum number of the food sources. Each employed bee, whose total

number equals to the the number of food sources, produces a

new food source in her food source site as given in (4).

ISBN: 978-988-19253-1-2

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ij

better source while each onlooker bee whose total number is equal to the number of employed bees selects a food source with the probability as given in (5). pi?fiti

(5) SN ?fitj

j?1

where fiti is the fitness of the solution xij and produces a new source in selected food source site by (4). After all onlookers are distributed to the sources, sources are checked whether they are to be abandoned. The employed bee associated with the abandoned source becomes a scout and makes random search in problem domain by (6). The best food source found so far has been memorized and the production steps are repeated until the stopping criterion is met [14]. xij?xminj?(xmaxj?xminj

)*rand (6) III. DESIGN PROCEDURE FOR DIFFERENTIAL AMPLIFIER The differential amplifier is one of the most versatile analog circuits and serves as the input stage to most operational amplifiers [3,15-16]. The problem considered here is the optimal selection of CMOS transistor dimensions and bias current for differential amplifier with current mirror

load (Fig.1), which is only a part of a complete analog circuit CAD tool.

It can be characterized by a number of specifications [15,16] such as common mode rejection ratio (CMRR), slew rate (SR), power dissipation (Pdiss), small signal characteristics (Av , f-3dB ), input common mode range (ICMR), power supply rejection ratio (PSRR)

Fig. 1. Differential amplifier with current mirror load [3,15-16]

In this work, performance metrics as well as design objective which can be defined as CF is the minimization of the occupied MOS transistor area as in (7).

?T

CF??

W(i)xL(i)?

(7) i?1

WCECS 2013

Proceedings of the World Congress on Engineering and Computer Science 2013 Vol II WCECS 2013, 23-25 October, 2013, San Francisco, USA

In order to ensure that all design constraints of small-signal differential voltage gain (Av), cutoff frequency (f-3dB), maximum and minimum input common mode voltages (VIC(max), VIC(min)), slew rate (SR), power dissipation (Pdiss) and design variables of output capacitance (CL) and MOS device sizes meet the desired bounds, general design procedure can be summarized below [15]:

? Determine range of Id5 (Iss) to satisfy the slew rate (SR) and power dissipation (Pdiss).

Idmin<Id5<Idmax (8)

Idmax=Pdiss/(VDD+|VSS|) (9)

DE, HS and ABC are utilized for a differential amplifier with current mirror load having design specifications of SR≥10V/μs, f0≥100kHz (CL=5pF), -1.25V≤ICMR≤1.25V, Av>100 V/V, Pdiss≤2mW, with PSO inputs of VDD=-VSS=2.5V, Vtn=0.4761V, Vtp=-0.6513V, K’n=181.2μA/V2, K’p= 65.8μA/V2. Constraints for design variables are set as, 100≥(W/L)i≥1.5 MOSFET length values are chosen as Li=1.4 μm where (i=1,…,6).

All design constraints can be employed as a vector in HS, DE, ABC given in (14).

x = [SR, Av, f-3dB, Vicmin, Vicmax, Pdiss] (14)

Simulations are performed in MATLAB environment Idmin?maxSRxCL,2/ ??2?f?3dBCL??? ???n??p? x 1/

with Intel Core 2 Duo CPU, T7300 @ 2.00GHz. Target

(10) value of CF is aimed to be smaller than 3x10-10m2. DE based

? Design W1/L1 (W2/L2) to satisfy Av design method resulted in a total MOS transistor area of 0.767x10-10 m2 along with exact values of design parameters

1/2

?K1'W1? (11) (Wi/Li, Ibias) as given in Table I. Design parameters obtained voutgmd(K1'IssW1/L1)1/22

Av??????

with each EA method are them used for sizing of CMOS vidgds2?gds4(?2??4)(Iss/2)(?2??4)?IssL1?

differential amplifier. SPICE simulation results of EA based

CMOS differential amplifier design are given in Figs. 2-4. ? Design W3/L3 (W4/L4) to satisfy the upper ICMR

Algorithm parameters and computational performance for

VIC (max) =VDD-VSG3+VTN1 (12) EA methods are shown in Table II. Despite the fact that DE

resulted in shortest computation time, minimum MOS

transistor area is obtained with HS method when compared ? Design W5/L5 (W6/L6) to satisfy the lower ICMR

with DE, ABC and previous work. Among the EA methods,

VIC (min) =VSS + VDS5 (sat) +VGS1= VSS + VDS5 (sat) +VGS2 (13) ABC provides better performances in terms of gain and

power dissipation as given in Table III. Simulation results

? Obtain exact values of design variables and iterate if show that DE, HS and ABC resulted in shorter constraints have not been satisfied and design objective(s) computational time than PSO. ICMR and cut-off frequency

values of DE and ABC based design method are also has (have) not been met.

improved when compared to that of PSO.

IV. SIMULATION RESULTS

TABLE I. DESIGN PARAMETERS OBTAINED WITH EA METHODS

The aim of this study is to minimize total CMOS

Design PSO

transistor area while satisfying design criteria and design Parameters [3]

variable constraints. Establishing design criteria and design variables to EA methods, the optimal circuit sizing was W1/L1,2/L2

aimed to be determined the algorithm. Design problem has (μm/μm)

been introduced by composing an equation consists of input W3/L3,W4/L4

variables and design variables as a CF. The starting point of (μm/μm) design consists of two types of information. First type of W5/L5,W6/L6

(μm/μm) information such as the technology and the power supply is

set by the designer. The other type is the design criteria. The

range of each criteria and design variable, power supply

TABLE II. COMPARISON OF COMPUTATIONAL PERFORMANCE

values and technology information is set as an input to EA

PSO

methods and DE, HS and ABC should obtain the solution set [3]

that consists the exact values of design variables (W/L)i

25.02 s 0.25 s 0.438 s 0.026 s Time

where (i1,…,6) and design criteria (f-3dB, VIC(max),

582 1000 500 6 Iterations

VIC(min), SR, Pdiss, Av) for given ranges. The design is implemented with the relationships that describe design NP=10=6 NP=10 NP=20 specifications to solve for DC currents and W/L values of all

Algorith

Parameters c1=c2=1.7 HMCR= CR=1 FN=10

0.9

provided in the previous section. Simulations are performed